SEMINARS AND WORKSHOPS
Workshop-Clock Tree Synthesis and Timing Optimization Techniques
Department of ECE had organized Hands On Workshop On Clock Tree Synthesis And Timing Optimization Techniques on 14/11/2024. The resource person for the workshop was Mr. L Shivashankar,Associate Design Engineer, Insemi Technology Pvt. Ltd,Bengaluru.The session successfully covered the key aspects of CTS and timing optimization techniques essential in modern VLSI design. The techniques applied in the lab demonstrated how effective CTS and timing adjustments ensure optimal performance, power, and reliability in integrated circuits. These practices are invaluable for students and professionals aiming to refine their skills in VLSI design and meet the stringent demands of advanced IC technologies.
