SEMINARS AND WORKSHOPS

A workshop on UNIVERSAL VERIFICATION METHODOLOGY was organized on 24/04/2023 which provided hands-on experience in designing a 16-bit ALU using Verilog, participants honed their skills in hardware description languages and gained a profound understanding of the intricacies involved in creating complex digital circuits. The project implementation phase challenged students to optimize the ALU for speed while minimizing resource utilization, fostering a deep appreciation for the delicate balance between performance and efficiency in VLSI design.