SEMINARS AND WORKSHOPS
DIGITAL MEMORY DESIGN WITH HANDS-ON RTL VERILOG HDL
Date :18-01-2024
Duration :11 am-5 pm
Workshop topic : Digital Memory Design with Hands-on RTL Verilog HDL
Number of Participants :24
Resource person :Mr Madan Gopal. M (Persuing Ph.D VLSI HLS FPGA ), Director and Corporate Trainer, VLSIT&P Services Private Limited. www.vlsitnp.co.in
On January 18th, 2024, a comprehensive workshop on “Digital Memory Design with Hands-on RTL Verilog HDL” was conducted in the VLSI Lab. The workshop was aimed at 5th-semester students, providing them with a deep dive into digital memory design and practical experience with RTL Verilog HDL. Mr. Madan Gopal. M, pursuing a Ph.D. in VLSI HLS FPGA and serving as the Director and Corporate Trainer at VLSIT&P Services Private Limited, was the resource person for the workshop.
The workshop covered a range of topics essential for understanding digital systems. Mr. Madan Gopal shared insights into effective debugging techniques, Real-world examples of Register-Transfer Level (RTL) designs were discussed, providing participants with practical exposure. Finite State Machine (FSM) design principles were covered with practical examples, aiding in the understanding of sequential logic. The workshop concluded with a detailed session on RTL memory modeling, a crucial aspect of digital memory design.
